IEC 60424-8-2015 pdf free download.Ferrite cores – Guidelines on the limits of surface irregularities – Part 8: PQ-cores.
4 Limits of surface irregularities
4.1 Chips and ragged edges
4.1.1 Chips and ragged edges located on the mating surface
The areas of the chips located on the mating surface (see Cl and Cl’ irregularities in Figure 2) shall not exceed the following limits:
— the cumulative area of the chips located on the mating surface shall be less than 4 % of the total mating surface;
— the cumulative area of the chips located on the centre post mating surface shall be less than 2 % of the total mating surface,
— the cumulative area of the chips located on the mating surface of one outer leg shall be less than 1 % of the total mating surface:
The total length of the ragged edges shall be less than 25 % of the perimeter of the relevant mating surface.
4.1.2 Chips located on other surfaces
The areas of the chips located on the other surfaces (see C2, C2. C3 and C3’ irregularities in Figure 2) shall not exceed the following limits:
— the allowable chipping areas are doubled as compared to the limits for the whole mating surfaces (see Table 1);
— the rule for the ragged edges is the same as for the mating surfaces;
— chips and ragged edges are not acceptable on the inner edges of the wire slot area.
4.2 Cracks
Figure 3 shows examples of cracks location on PQ-cores:
a single crack which intersects the perimeter of the relevant surface at two points is not acceptable (see S1 in Figure 3);
the number of the cracks located on the same surface shall not exceed 3.
The limits of cracks at various locations shown in Figure 3 are given in Table 3.IEC 60424-8 pdf download.